Definition in file at86rf212.h.
Go to the source code of this file.
Defines | |
| #define | AT86RF212_H (1) |
| #define | BUSY_RX (1) |
| #define | BUSY_RX_AACK (17) |
| #define | BUSY_RX_AACK_NOCLK (30) |
| #define | BUSY_TX (2) |
| #define | BUSY_TX_ARET (18) |
| #define | CLKM_16MHz (5) |
| #define | CLKM_1MHz (1) |
| #define | CLKM_2mA (0) |
| #define | CLKM_2MHz (2) |
| #define | CLKM_4mA (1) |
| #define | CLKM_4MHz (3) |
| #define | CLKM_6mA (2) |
| #define | CLKM_8mA (3) |
| #define | CLKM_8MHz (4) |
| #define | CLKM_no_clock (0) |
| #define | CMD_FORCE_TRX_OFF (3) |
| #define | CMD_NOP (0) |
| #define | CMD_PLL_ON (9) |
| #define | CMD_RX_AACK_ON (22) |
| #define | CMD_RX_ON (6) |
| #define | CMD_TRX_OFF (8) |
| #define | CMD_TX_ARET_ON (25) |
| #define | CMD_TX_START (2) |
| #define | P_ON (0) |
| #define | PLL_ON (9) |
| #define | RADIO_NAME "AT86RF212" |
| #define | RADIO_PART_NUM (RF212A_PART_NUM) |
| #define | RADIO_VERSION_NUM (RF212A_VERSION_NUM) |
| #define | RATE_CODE_BPSK20 (0) |
| #define | RATE_CODE_BPSK40 (4) |
| #define | RATE_CODE_NONE (255) |
| #define | RATE_CODE_OQPSK100 (8) |
| #define | RATE_CODE_OQPSK1000 (14) |
| #define | RATE_CODE_OQPSK1000_1 (15) |
| #define | RATE_CODE_OQPSK200 (9) |
| #define | RATE_CODE_OQPSK250 (12) |
| #define | RATE_CODE_OQPSK400 (10) |
| #define | RATE_CODE_OQPSK400_1 (11) |
| #define | RATE_CODE_OQPSK500 (13) |
| #define | RF212A_PART_NUM (7) |
| #define | RF212A_VERSION_NUM (1) |
| #define | RG_ANT_DIV (0xd) |
| #define | RG_BATMON (0x11) |
| #define | RG_CC_CTRL_0 (0x13) |
| #define | RG_CC_CTRL_1 (0x14) |
| #define | RG_CCA_THRES (0x9) |
| #define | RG_CSMA_BE (0x2f) |
| #define | RG_CSMA_SEED_0 (0x2d) |
| #define | RG_CSMA_SEED_1 (0x2e) |
| #define | RG_FTN_CTRL (0x18) |
| #define | RG_IEEE_ADDR_0 (0x24) |
| #define | RG_IEEE_ADDR_1 (0x25) |
| #define | RG_IEEE_ADDR_2 (0x26) |
| #define | RG_IEEE_ADDR_3 (0x27) |
| #define | RG_IEEE_ADDR_4 (0x28) |
| #define | RG_IEEE_ADDR_5 (0x29) |
| #define | RG_IEEE_ADDR_6 (0x2a) |
| #define | RG_IEEE_ADDR_7 (0x2b) |
| #define | RG_IRQ_MASK (0xe) |
| #define | RG_IRQ_STATUS (0xf) |
| #define | RG_MAN_ID_0 (0x1e) |
| #define | RG_MAN_ID_1 (0x1f) |
| #define | RG_PAN_ID_0 (0x22) |
| #define | RG_PAN_ID_1 (0x23) |
| #define | RG_PART_NUM (0x1c) |
| #define | RG_PHY_CC_CCA (0x8) |
| #define | RG_PHY_ED_LEVEL (0x7) |
| #define | RG_PHY_RSSI (0x6) |
| #define | RG_PHY_TX_PWR (0x5) |
| #define | RG_PLL_CF (0x1a) |
| #define | RG_PLL_DCU (0x1b) |
| #define | RG_RF_CTRL_0 (0x16) |
| #define | RG_RF_CTRL_1 (0x19) |
| #define | RG_RX_SYN (0x15) |
| #define | RG_SFD_VALUE (0xb) |
| #define | RG_SHORT_ADDR_0 (0x20) |
| #define | RG_SHORT_ADDR_1 (0x21) |
| #define | RG_TRX_CTRL_0 (0x3) |
| #define | RG_TRX_CTRL_1 (0x4) |
| #define | RG_TRX_CTRL_2 (0xc) |
| #define | RG_TRX_STATE (0x2) |
| #define | RG_TRX_STATUS (0x1) |
| #define | RG_VERSION_NUM (0x1d) |
| #define | RG_VREG_CTRL (0x10) |
| #define | RG_XAH_CTRL_0 (0x2c) |
| #define | RG_XAH_CTRL_1 (0x17) |
| #define | RG_XOSC_CTRL (0x12) |
| #define | RX_AACK_ON (22) |
| #define | RX_AACK_ON_NOCLK (29) |
| #define | RX_ON (6) |
| #define | RX_ON_NOCLK (28) |
| #define | SLEEP (15) |
| #define | SR_AACK_ACK_TIME 0x17,0x4,2 |
| #define | SR_AACK_DIS_ACK 0x2e,0x10,4 |
| #define | SR_AACK_FLTR_RES_FT 0x17,0x20,5 |
| #define | SR_AACK_FVN_MODE 0x2e,0xc0,6 |
| #define | SR_AACK_I_AM_COORD 0x2e,0x8,3 |
| #define | SR_AACK_PROM_MODE 0x17,0x3,0 |
| #define | SR_AACK_SET_PD 0x2e,0x20,5 |
| #define | SR_AACK_UPLD_RES_FT 0x17,0x10,4 |
| #define | SR_AMI 0xf,0x20,5 |
| #define | SR_ANT_CTRL 0xd,0x3,0 |
| #define | SR_ANT_EXT_SW_EN 0xd,0x4,2 |
| #define | SR_ANT_SEL 0xd,0x80,7 |
| #define | SR_AVDD_OK 0x10,0x40,6 |
| #define | SR_AVREG_EXT 0x10,0x80,7 |
| #define | SR_BAT_LOW 0xf,0x80,7 |
| #define | SR_BATMON_HR 0x11,0x10,4 |
| #define | SR_BATMON_OK 0x11,0x20,5 |
| #define | SR_BATMON_VTH 0x11,0xf,0 |
| #define | SR_BPSK_OQPSK 0xc,0x8,3 |
| #define | SR_CC_ 0x14,0x3,0 |
| #define | SR_CC_BAND 0x14,0x4,2 |
| #define | SR_CC_NUMBER 0x13,0xff,0 |
| #define | SR_CCA_DONE 0x1,0x80,7 |
| #define | SR_CCA_ED_READY 0xf,0x10,4 |
| #define | SR_CCA_ED_THRES 0x9,0xf,0 |
| #define | SR_CCA_MODE 0x8,0x60,5 |
| #define | SR_CCA_REQUEST 0x8,0x80,7 |
| #define | SR_CCA_STATUS 0x1,0x40,6 |
| #define | SR_CHANNEL 0x8,0x1f,0 |
| #define | SR_CLKM_CTRL 0x3,0x7,0 |
| #define | SR_CLKM_SHA_SEL 0x3,0x8,3 |
| #define | SR_CSMA_LBT_MODE 0x17,0x80,7 |
| #define | SR_CSMA_SEED_0 0x2d,0xff,0 |
| #define | SR_CSMA_SEED_1 0x2e,0x7,0 |
| #define | SR_DVDD_OK 0x10,0x4,2 |
| #define | SR_DVREG_EXT 0x10,0x8,3 |
| #define | SR_ED_LEVEL 0x7,0xff,0 |
| #define | SR_FTN_START 0x18,0x80,7 |
| #define | SR_GC_PA 0x5,0x60,5 |
| #define | SR_GC_TX_OFFS 0x16,0x3,0 |
| #define | SR_IEEE_ADDR_0 0x24,0xff,0 |
| #define | SR_IEEE_ADDR_1 0x25,0xff,0 |
| #define | SR_IEEE_ADDR_2 0x26,0xff,0 |
| #define | SR_IEEE_ADDR_3 0x27,0xff,0 |
| #define | SR_IEEE_ADDR_4 0x28,0xff,0 |
| #define | SR_IEEE_ADDR_5 0x29,0xff,0 |
| #define | SR_IEEE_ADDR_6 0x2a,0xff,0 |
| #define | SR_IEEE_ADDR_7 0x2b,0xff,0 |
| #define | SR_IRQ_2_EXT_EN 0x4,0x40,6 |
| #define | SR_IRQ_MASK_MODE 0x4,0x3,0 |
| #define | SR_MAN_ID_0 0x1e,0xff,0 |
| #define | SR_MAN_ID_1 0x1f,0xff,0 |
| #define | SR_MASK_AMI 0xe,0x20,5 |
| #define | SR_MASK_BAT_LOW 0xe,0x80,7 |
| #define | SR_MASK_CCA_ED_READY 0xe,0x10,4 |
| #define | SR_MASK_PLL_UNLOCK 0xe,0x3,0 |
| #define | SR_MASK_RX_START 0xe,0x4,2 |
| #define | SR_MASK_TRX_END 0xe,0x8,3 |
| #define | SR_MASK_TRX_UR 0xe,0x40,6 |
| #define | SR_MAX_BE 0x2f,0xf0,4 |
| #define | SR_MAX_CSMA_RETRIES 0x2c,0xf,0 |
| #define | SR_MAX_FRAME_RETRIES 0x2c,0xf0,4 |
| #define | SR_MIN_BE 0x2f,0xf,0 |
| #define | SR_OQPSK_DATA_RATE 0xc,0x3,0 |
| #define | SR_PA_BOOST 0x5,0x80,7 |
| #define | SR_PA_EXT_EN 0x4,0x80,7 |
| #define | SR_PA_LT 0x16,0xc0,6 |
| #define | SR_PAD_IO 0x3,0xc0,6 |
| #define | SR_PAD_IO_CLKM 0x3,0x30,4 |
| #define | SR_PAN_ID_0 0x22,0xff,0 |
| #define | SR_PAN_ID_1 0x23,0xff,0 |
| #define | SR_PART_NUM 0x1c,0xff,0 |
| #define | SR_PLL_CF_START 0x1a,0x80,7 |
| #define | SR_PLL_DCU_START 0x1b,0x80,7 |
| #define | SR_PLL_UNLOCK 0xf,0x3,0 |
| #define | SR_RF_MC 0x19,0xf0,4 |
| #define | SR_RND_VALUE 0x6,0x60,5 |
| #define | SR_RSSI 0x6,0x1f,0 |
| #define | SR_RX_BL_CTRL 0x4,0x10,4 |
| #define | SR_RX_CRC_VALID 0x6,0x80,7 |
| #define | SR_RX_PDT_DIS 0x15,0x80,7 |
| #define | SR_RX_PDT_LEVEL 0x15,0xf,0 |
| #define | SR_RX_SAFE_MODE 0xc,0x80,7 |
| #define | SR_RX_START 0xf,0x4,2 |
| #define | SR_SFD_VALUE 0xb,0xff,0 |
| #define | SR_SHORT_ADDR_0 0x20,0xff,0 |
| #define | SR_SHORT_ADDR_1 0x21,0xff,0 |
| #define | SR_SPI_CMD_MODE 0x4,0xc,2 |
| #define | SR_SUB_MODE 0xc,0x4,2 |
| #define | SR_TRAC_STATUS 0x2,0xe0,5 |
| #define | SR_TRX_CMD 0x2,0x1f,0 |
| #define | SR_TRX_END 0xf,0x8,3 |
| #define | SR_TRX_OFF_AVDD_EN 0xc,0x40,6 |
| #define | SR_TRX_STATUS 0x1,0x1f,0 |
| #define | SR_TRX_UR 0xf,0x40,6 |
| #define | SR_TX_AUTO_CRC_ON 0x4,0x20,5 |
| #define | SR_TX_PWR 0x5,0x1f,0 |
| #define | SR_VERSION_NUM 0x1d,0xff,0 |
| #define | SR_XTAL_MODE 0x12,0xf0,4 |
| #define | SR_XTAL_TRIM 0x12,0xf,0 |
| #define | TRAC_CHANNEL_ACCESS_FAILURE (3) |
| #define | TRAC_CHANNEL_ACCESS_FAILURE (3) |
| #define | TRAC_INVALID (7) |
| #define | TRAC_NO_ACK (5) |
| #define | TRAC_NO_ACK (5) |
| #define | TRAC_SUCCESS (0) |
| #define | TRAC_SUCCESS (0) |
| #define | TRAC_SUCCESS_DATA_PENDING (1) |
| #define | TRAC_SUCCESS_WAIT_FOR_ACK (2) |
| #define | TRX_CCA_TIME_US (140) |
| #define | TRX_CMD_FR (_BV(5)) |
| #define | TRX_CMD_FW (_BV(6) | _BV(5)) |
| #define | TRX_CMD_RADDR_MASK (0x3f) |
| #define | TRX_CMD_RR (_BV(7)) |
| #define | TRX_CMD_RW (_BV(7) | _BV(6)) |
| #define | TRX_CMD_SR (0) |
| #define | TRX_CMD_SW (_BV(6)) |
| #define | TRX_INIT_TIME_US (510) |
| #define | TRX_IRQ_AMI _BV(5) |
| #define | TRX_IRQ_BAT_LOW _BV(7) |
| #define | TRX_IRQ_CCA_ED _BV(4) |
| #define | TRX_IRQ_PLL_LOCK _BV(0) |
| #define | TRX_IRQ_PLL_UNLOCK _BV(1) |
| #define | TRX_IRQ_RX_START _BV(2) |
| #define | TRX_IRQ_TRX_END _BV(3) |
| #define | TRX_IRQ_UR _BV(6) |
| #define | TRX_MAX_CHANNEL (10) |
| #define | TRX_MIN_CHANNEL (0) |
| #define | TRX_NB_CHANNELS (11) |
| #define | TRX_OFF (8) |
| #define | TRX_PLL_LOCK_TIME_US (180) |
| #define | TRX_RESET_TIME_US (6) |
| #define | TRX_SUPPORTED_CHANNELS (0x00007ffUL) |
| Mask for supported channels of this radio. The AT86RF212 supports channels 0 ... 10 of IEEE 802.15.4 (currently no support for free configurable frequencies here). | |
| #define | TRX_SUPPORTED_PAGES (42) |
| Mask for supported channel pages (a.k.a. modulation schemes) of this radio. The AT86RF230 supports channel page ???? OQPSK_250. | |
| #define | TRX_SUPPORTS_BAND_700 (1) |
| #define | TRX_SUPPORTS_BAND_800 (1) |
| #define | TRX_SUPPORTS_BAND_900 (1) |
| #define | TX_ARET_ON (25) |
Typedefs | |
| typedef uint8_t | trx_ramaddr_t |
| typedef uint8_t | trx_regaddr_t |
| typedef uint8_t | trx_regval_t |
| #define RADIO_NAME "AT86RF212" |
name string of the radio
Definition at line 383 of file at86rf212.h.
| #define RADIO_PART_NUM (RF212A_PART_NUM) |
contents of the RG_PART_NUM register
Definition at line 385 of file at86rf212.h.
| #define RADIO_VERSION_NUM (RF212A_VERSION_NUM) |
contents of the RG_VERSION_NUM register
Definition at line 387 of file at86rf212.h.
| #define RATE_CODE_BPSK20 (0) |
Rate code for BPSK20, xx kchip/s, yy kbit/s
Definition at line 475 of file at86rf212.h.
| #define RATE_CODE_BPSK40 (4) |
Rate code for BPSK40, xx kchip/s, yy kbit/s
Definition at line 478 of file at86rf212.h.
| #define RATE_CODE_NONE (255) |
undefined data rate
Definition at line 500 of file at86rf212.h.
| #define RATE_CODE_OQPSK100 (8) |
Rate code for OQPSK100, xx kchip/s, yy kbit/s
Definition at line 481 of file at86rf212.h.
| #define RATE_CODE_OQPSK1000 (14) |
Rate code for OQPSK1000, xx kchip/s, yy kbit/s
Definition at line 497 of file at86rf212.h.
| #define RATE_CODE_OQPSK200 (9) |
Rate code for OQPSK200, xx kchip/s, yy kbit/s
Definition at line 484 of file at86rf212.h.
| #define RATE_CODE_OQPSK250 (12) |
Rate code for OQPSK250, xx kchip/s, yy kbit/s
Definition at line 491 of file at86rf212.h.
| #define RATE_CODE_OQPSK400 (10) |
Rate code for OQPSK400, xx kchip/s, yy kbit/s
Definition at line 487 of file at86rf212.h.
| #define RATE_CODE_OQPSK500 (13) |
Rate code for OQPSK500, xx kchip/s, yy kbit/s
Definition at line 494 of file at86rf212.h.
| #define RG_ANT_DIV (0xd) |
Offset for register ANT_DIV
Definition at line 175 of file at86rf212.h.
| #define RG_BATMON (0x11) |
Offset for register BATMON
Definition at line 225 of file at86rf212.h.
| #define RG_CC_CTRL_0 (0x13) |
Offset for register CC_CTRL_0
Definition at line 239 of file at86rf212.h.
| #define RG_CC_CTRL_1 (0x14) |
Offset for register CC_CTRL_1
Definition at line 243 of file at86rf212.h.
| #define RG_CCA_THRES (0x9) |
Offset for register CCA_THRES
Definition at line 155 of file at86rf212.h.
| #define RG_CSMA_BE (0x2f) |
Offset for register CSMA_BE
Definition at line 377 of file at86rf212.h.
| #define RG_CSMA_SEED_0 (0x2d) |
Offset for register CSMA_SEED_0
Definition at line 361 of file at86rf212.h.
| #define RG_CSMA_SEED_1 (0x2e) |
Offset for register CSMA_SEED_1
Definition at line 365 of file at86rf212.h.
| #define RG_FTN_CTRL (0x18) |
Offset for register FTN_CTRL
Definition at line 273 of file at86rf212.h.
| #define RG_IEEE_ADDR_0 (0x24) |
Offset for register IEEE_ADDR_0
Definition at line 323 of file at86rf212.h.
| #define RG_IEEE_ADDR_1 (0x25) |
Offset for register IEEE_ADDR_1
Definition at line 327 of file at86rf212.h.
| #define RG_IEEE_ADDR_2 (0x26) |
Offset for register IEEE_ADDR_2
Definition at line 331 of file at86rf212.h.
| #define RG_IEEE_ADDR_3 (0x27) |
Offset for register IEEE_ADDR_3
Definition at line 335 of file at86rf212.h.
| #define RG_IEEE_ADDR_4 (0x28) |
Offset for register IEEE_ADDR_4
Definition at line 339 of file at86rf212.h.
| #define RG_IEEE_ADDR_5 (0x29) |
Offset for register IEEE_ADDR_5
Definition at line 343 of file at86rf212.h.
| #define RG_IEEE_ADDR_6 (0x2a) |
Offset for register IEEE_ADDR_6
Definition at line 347 of file at86rf212.h.
| #define RG_IEEE_ADDR_7 (0x2b) |
Offset for register IEEE_ADDR_7
Definition at line 351 of file at86rf212.h.
| #define RG_IRQ_MASK (0xe) |
Offset for register IRQ_MASK
Definition at line 183 of file at86rf212.h.
| #define RG_IRQ_STATUS (0xf) |
Offset for register IRQ_STATUS
Definition at line 199 of file at86rf212.h.
| #define RG_MAN_ID_0 (0x1e) |
Offset for register MAN_ID_0
Definition at line 299 of file at86rf212.h.
| #define RG_MAN_ID_1 (0x1f) |
Offset for register MAN_ID_1
Definition at line 303 of file at86rf212.h.
| #define RG_PAN_ID_0 (0x22) |
Offset for register PAN_ID_0
Definition at line 315 of file at86rf212.h.
| #define RG_PAN_ID_1 (0x23) |
Offset for register PAN_ID_1
Definition at line 319 of file at86rf212.h.
| #define RG_PART_NUM (0x1c) |
Offset for register PART_NUM
Definition at line 289 of file at86rf212.h.
| #define RG_PHY_CC_CCA (0x8) |
Offset for register PHY_CC_CCA
Definition at line 147 of file at86rf212.h.
| #define RG_PHY_ED_LEVEL (0x7) |
Offset for register PHY_ED_LEVEL
Definition at line 143 of file at86rf212.h.
| #define RG_PHY_RSSI (0x6) |
Offset for register PHY_RSSI
Definition at line 135 of file at86rf212.h.
| #define RG_PHY_TX_PWR (0x5) |
Offset for register PHY_TX_PWR
Definition at line 127 of file at86rf212.h.
| #define RG_PLL_CF (0x1a) |
Offset for register PLL_CF
Definition at line 281 of file at86rf212.h.
| #define RG_PLL_DCU (0x1b) |
Offset for register PLL_DCU
Definition at line 285 of file at86rf212.h.
| #define RG_RF_CTRL_0 (0x16) |
Offset for register RF_CTRL_0
Definition at line 255 of file at86rf212.h.
| #define RG_RF_CTRL_1 (0x19) |
Offset for register RF_CTRL_1
Definition at line 277 of file at86rf212.h.
| #define RG_RX_SYN (0x15) |
Offset for register RX_SYN
Definition at line 249 of file at86rf212.h.
| #define RG_SFD_VALUE (0xb) |
Offset for register SFD_VALUE
Definition at line 159 of file at86rf212.h.
| #define RG_SHORT_ADDR_0 (0x20) |
Offset for register SHORT_ADDR_0
Definition at line 307 of file at86rf212.h.
| #define RG_SHORT_ADDR_1 (0x21) |
Offset for register SHORT_ADDR_1
Definition at line 311 of file at86rf212.h.
| #define RG_TRX_CTRL_0 (0x3) |
Offset for register TRX_CTRL_0
Definition at line 93 of file at86rf212.h.
| #define RG_TRX_CTRL_1 (0x4) |
Offset for register TRX_CTRL_1
Definition at line 113 of file at86rf212.h.
| #define RG_TRX_CTRL_2 (0xc) |
Offset for register TRX_CTRL_2
Definition at line 163 of file at86rf212.h.
| #define RG_TRX_STATE (0x2) |
Offset for register TRX_STATE
Definition at line 73 of file at86rf212.h.
| #define RG_TRX_STATUS (0x1) |
Offset for register TRX_STATUS
Definition at line 51 of file at86rf212.h.
| #define RG_VERSION_NUM (0x1d) |
Offset for register VERSION_NUM
Definition at line 294 of file at86rf212.h.
| #define RG_VREG_CTRL (0x10) |
Offset for register VREG_CTRL
Definition at line 215 of file at86rf212.h.
| #define RG_XAH_CTRL_0 (0x2c) |
Offset for register XAH_CTRL_0
Definition at line 355 of file at86rf212.h.
| #define RG_XAH_CTRL_1 (0x17) |
Offset for register XAH_CTRL_1
Definition at line 261 of file at86rf212.h.
| #define RG_XOSC_CTRL (0x12) |
Offset for register XOSC_CTRL
Definition at line 233 of file at86rf212.h.
| #define SR_AACK_ACK_TIME 0x17,0x4,2 |
Access parameters for sub-register AACK_ACK_TIME in register XAH_CTRL_1
Definition at line 269 of file at86rf212.h.
| #define SR_AACK_DIS_ACK 0x2e,0x10,4 |
Access parameters for sub-register AACK_DIS_ACK in register CSMA_SEED_1
Definition at line 371 of file at86rf212.h.
| #define SR_AACK_FLTR_RES_FT 0x17,0x20,5 |
Access parameters for sub-register AACK_FLTR_RES_FT in register XAH_CTRL_1
Definition at line 265 of file at86rf212.h.
| #define SR_AACK_FVN_MODE 0x2e,0xc0,6 |
Access parameters for sub-register AACK_FVN_MODE in register CSMA_SEED_1
Definition at line 367 of file at86rf212.h.
| #define SR_AACK_I_AM_COORD 0x2e,0x8,3 |
Access parameters for sub-register AACK_I_AM_COORD in register CSMA_SEED_1
Definition at line 373 of file at86rf212.h.
| #define SR_AACK_PROM_MODE 0x17,0x3,0 |
Access parameters for sub-register AACK_PROM_MODE in register XAH_CTRL_1
Definition at line 271 of file at86rf212.h.
| #define SR_AACK_SET_PD 0x2e,0x20,5 |
Access parameters for sub-register AACK_SET_PD in register CSMA_SEED_1
Definition at line 369 of file at86rf212.h.
| #define SR_AACK_UPLD_RES_FT 0x17,0x10,4 |
Access parameters for sub-register AACK_UPLD_RES_FT in register XAH_CTRL_1
Definition at line 267 of file at86rf212.h.
| #define SR_AMI 0xf,0x20,5 |
Access parameters for sub-register AMI in register IRQ_STATUS
Definition at line 205 of file at86rf212.h.
| #define SR_ANT_CTRL 0xd,0x3,0 |
Access parameters for sub-register ANT_CTRL in register ANT_DIV
Definition at line 181 of file at86rf212.h.
| #define SR_ANT_EXT_SW_EN 0xd,0x4,2 |
Access parameters for sub-register ANT_EXT_SW_EN in register ANT_DIV
Definition at line 179 of file at86rf212.h.
| #define SR_ANT_SEL 0xd,0x80,7 |
Access parameters for sub-register ANT_SEL in register ANT_DIV
Definition at line 177 of file at86rf212.h.
| #define SR_AVDD_OK 0x10,0x40,6 |
Access parameters for sub-register AVDD_OK in register VREG_CTRL
Definition at line 219 of file at86rf212.h.
| #define SR_AVREG_EXT 0x10,0x80,7 |
Access parameters for sub-register AVREG_EXT in register VREG_CTRL
Definition at line 217 of file at86rf212.h.
| #define SR_BAT_LOW 0xf,0x80,7 |
Access parameters for sub-register BAT_LOW in register IRQ_STATUS
Definition at line 201 of file at86rf212.h.
| #define SR_BATMON_HR 0x11,0x10,4 |
Access parameters for sub-register BATMON_HR in register BATMON
Definition at line 229 of file at86rf212.h.
| #define SR_BATMON_OK 0x11,0x20,5 |
Access parameters for sub-register BATMON_OK in register BATMON
Definition at line 227 of file at86rf212.h.
| #define SR_BATMON_VTH 0x11,0xf,0 |
Access parameters for sub-register BATMON_VTH in register BATMON
Definition at line 231 of file at86rf212.h.
| #define SR_BPSK_OQPSK 0xc,0x8,3 |
Access parameters for sub-register BPSK_OQPSK in register TRX_CTRL_2
Definition at line 169 of file at86rf212.h.
| #define SR_CC_ 0x14,0x3,0 |
Access parameters for sub-register CC_ in register CC_CTRL_1
Definition at line 247 of file at86rf212.h.
| #define SR_CC_BAND 0x14,0x4,2 |
Access parameters for sub-register CC_BAND in register CC_CTRL_1
Definition at line 245 of file at86rf212.h.
| #define SR_CC_NUMBER 0x13,0xff,0 |
Access parameters for sub-register CC_NUMBER in register CC_CTRL_0
Definition at line 241 of file at86rf212.h.
| #define SR_CCA_DONE 0x1,0x80,7 |
Access parameters for sub-register CCA_DONE in register TRX_STATUS
Definition at line 53 of file at86rf212.h.
| #define SR_CCA_ED_READY 0xf,0x10,4 |
Access parameters for sub-register CCA_ED_READY in register IRQ_STATUS
Definition at line 207 of file at86rf212.h.
| #define SR_CCA_ED_THRES 0x9,0xf,0 |
Access parameters for sub-register CCA_ED_THRES in register CCA_THRES
Definition at line 157 of file at86rf212.h.
| #define SR_CCA_MODE 0x8,0x60,5 |
Access parameters for sub-register CCA_MODE in register PHY_CC_CCA
Definition at line 151 of file at86rf212.h.
| #define SR_CCA_REQUEST 0x8,0x80,7 |
Access parameters for sub-register CCA_REQUEST in register PHY_CC_CCA
Definition at line 149 of file at86rf212.h.
| #define SR_CCA_STATUS 0x1,0x40,6 |
Access parameters for sub-register CCA_STATUS in register TRX_STATUS
Definition at line 55 of file at86rf212.h.
| #define SR_CHANNEL 0x8,0x1f,0 |
Access parameters for sub-register CHANNEL in register PHY_CC_CCA
Definition at line 153 of file at86rf212.h.
| #define SR_CLKM_CTRL 0x3,0x7,0 |
Access parameters for sub-register CLKM_CTRL in register TRX_CTRL_0
Definition at line 105 of file at86rf212.h.
| #define SR_CLKM_SHA_SEL 0x3,0x8,3 |
Access parameters for sub-register CLKM_SHA_SEL in register TRX_CTRL_0
Definition at line 103 of file at86rf212.h.
| #define SR_CSMA_LBT_MODE 0x17,0x80,7 |
Access parameters for sub-register CSMA_LBT_MODE in register XAH_CTRL_1
Definition at line 263 of file at86rf212.h.
| #define SR_CSMA_SEED_0 0x2d,0xff,0 |
Access parameters for sub-register CSMA_SEED_0 in register CSMA_SEED_0
Definition at line 363 of file at86rf212.h.
| #define SR_CSMA_SEED_1 0x2e,0x7,0 |
Access parameters for sub-register CSMA_SEED_1 in register CSMA_SEED_1
Definition at line 375 of file at86rf212.h.
| #define SR_DVDD_OK 0x10,0x4,2 |
Access parameters for sub-register DVDD_OK in register VREG_CTRL
Definition at line 223 of file at86rf212.h.
| #define SR_DVREG_EXT 0x10,0x8,3 |
Access parameters for sub-register DVREG_EXT in register VREG_CTRL
Definition at line 221 of file at86rf212.h.
| #define SR_ED_LEVEL 0x7,0xff,0 |
Access parameters for sub-register ED_LEVEL in register PHY_ED_LEVEL
Definition at line 145 of file at86rf212.h.
| #define SR_FTN_START 0x18,0x80,7 |
Access parameters for sub-register FTN_START in register FTN_CTRL
Definition at line 275 of file at86rf212.h.
| #define SR_GC_PA 0x5,0x60,5 |
Access parameters for sub-register GC_PA in register PHY_TX_PWR
Definition at line 131 of file at86rf212.h.
| #define SR_GC_TX_OFFS 0x16,0x3,0 |
Access parameters for sub-register GC_TX_OFFS in register RF_CTRL_0
Definition at line 259 of file at86rf212.h.
| #define SR_IEEE_ADDR_0 0x24,0xff,0 |
Access parameters for sub-register IEEE_ADDR_0 in register IEEE_ADDR_0
Definition at line 325 of file at86rf212.h.
| #define SR_IEEE_ADDR_1 0x25,0xff,0 |
Access parameters for sub-register IEEE_ADDR_1 in register IEEE_ADDR_1
Definition at line 329 of file at86rf212.h.
| #define SR_IEEE_ADDR_2 0x26,0xff,0 |
Access parameters for sub-register IEEE_ADDR_2 in register IEEE_ADDR_2
Definition at line 333 of file at86rf212.h.
| #define SR_IEEE_ADDR_3 0x27,0xff,0 |
Access parameters for sub-register IEEE_ADDR_3 in register IEEE_ADDR_3
Definition at line 337 of file at86rf212.h.
| #define SR_IEEE_ADDR_4 0x28,0xff,0 |
Access parameters for sub-register IEEE_ADDR_4 in register IEEE_ADDR_4
Definition at line 341 of file at86rf212.h.
| #define SR_IEEE_ADDR_5 0x29,0xff,0 |
Access parameters for sub-register IEEE_ADDR_5 in register IEEE_ADDR_5
Definition at line 345 of file at86rf212.h.
| #define SR_IEEE_ADDR_6 0x2a,0xff,0 |
Access parameters for sub-register IEEE_ADDR_6 in register IEEE_ADDR_6
Definition at line 349 of file at86rf212.h.
| #define SR_IEEE_ADDR_7 0x2b,0xff,0 |
Access parameters for sub-register IEEE_ADDR_7 in register IEEE_ADDR_7
Definition at line 353 of file at86rf212.h.
| #define SR_IRQ_2_EXT_EN 0x4,0x40,6 |
Access parameters for sub-register IRQ_2_EXT_EN in register TRX_CTRL_1
Definition at line 117 of file at86rf212.h.
| #define SR_IRQ_MASK_MODE 0x4,0x3,0 |
Access parameters for sub-register IRQ_MASK_MODE in register TRX_CTRL_1
Definition at line 125 of file at86rf212.h.
| #define SR_MAN_ID_0 0x1e,0xff,0 |
Access parameters for sub-register MAN_ID_0 in register MAN_ID_0
Definition at line 301 of file at86rf212.h.
| #define SR_MAN_ID_1 0x1f,0xff,0 |
Access parameters for sub-register MAN_ID_1 in register MAN_ID_1
Definition at line 305 of file at86rf212.h.
| #define SR_MASK_AMI 0xe,0x20,5 |
Access parameters for sub-register MASK_AMI in register IRQ_MASK
Definition at line 189 of file at86rf212.h.
| #define SR_MASK_BAT_LOW 0xe,0x80,7 |
Access parameters for sub-register MASK_BAT_LOW in register IRQ_MASK
Definition at line 185 of file at86rf212.h.
| #define SR_MASK_CCA_ED_READY 0xe,0x10,4 |
Access parameters for sub-register MASK_CCA_ED_READY in register IRQ_MASK
Definition at line 191 of file at86rf212.h.
| #define SR_MASK_PLL_UNLOCK 0xe,0x3,0 |
Access parameters for sub-register MASK_PLL_UNLOCK in register IRQ_MASK
Definition at line 197 of file at86rf212.h.
| #define SR_MASK_RX_START 0xe,0x4,2 |
Access parameters for sub-register MASK_RX_START in register IRQ_MASK
Definition at line 195 of file at86rf212.h.
| #define SR_MASK_TRX_END 0xe,0x8,3 |
Access parameters for sub-register MASK_TRX_END in register IRQ_MASK
Definition at line 193 of file at86rf212.h.
| #define SR_MASK_TRX_UR 0xe,0x40,6 |
Access parameters for sub-register MASK_TRX_UR in register IRQ_MASK
Definition at line 187 of file at86rf212.h.
| #define SR_MAX_BE 0x2f,0xf0,4 |
Access parameters for sub-register MAX_BE in register CSMA_BE
Definition at line 379 of file at86rf212.h.
| #define SR_MAX_CSMA_RETRIES 0x2c,0xf,0 |
Access parameters for sub-register MAX_CSMA_RETRIES in register XAH_CTRL_0
Definition at line 359 of file at86rf212.h.
| #define SR_MAX_FRAME_RETRIES 0x2c,0xf0,4 |
Access parameters for sub-register MAX_FRAME_RETRIES in register XAH_CTRL_0
Definition at line 357 of file at86rf212.h.
| #define SR_MIN_BE 0x2f,0xf,0 |
Access parameters for sub-register MIN_BE in register CSMA_BE
Definition at line 381 of file at86rf212.h.
| #define SR_OQPSK_DATA_RATE 0xc,0x3,0 |
Access parameters for sub-register OQPSK_DATA_RATE in register TRX_CTRL_2
Definition at line 173 of file at86rf212.h.
| #define SR_PA_BOOST 0x5,0x80,7 |
Access parameters for sub-register PA_BOOST in register PHY_TX_PWR
Definition at line 129 of file at86rf212.h.
| #define SR_PA_EXT_EN 0x4,0x80,7 |
Access parameters for sub-register PA_EXT_EN in register TRX_CTRL_1
Definition at line 115 of file at86rf212.h.
| #define SR_PA_LT 0x16,0xc0,6 |
Access parameters for sub-register PA_LT in register RF_CTRL_0
Definition at line 257 of file at86rf212.h.
| #define SR_PAD_IO 0x3,0xc0,6 |
Access parameters for sub-register PAD_IO in register TRX_CTRL_0
Definition at line 95 of file at86rf212.h.
| #define SR_PAD_IO_CLKM 0x3,0x30,4 |
Access parameters for sub-register PAD_IO_CLKM in register TRX_CTRL_0
Definition at line 97 of file at86rf212.h.
| #define SR_PAN_ID_0 0x22,0xff,0 |
Access parameters for sub-register PAN_ID_0 in register PAN_ID_0
Definition at line 317 of file at86rf212.h.
| #define SR_PAN_ID_1 0x23,0xff,0 |
Access parameters for sub-register PAN_ID_1 in register PAN_ID_1
Definition at line 321 of file at86rf212.h.
| #define SR_PART_NUM 0x1c,0xff,0 |
Access parameters for sub-register PART_NUM in register PART_NUM
Definition at line 291 of file at86rf212.h.
| #define SR_PLL_CF_START 0x1a,0x80,7 |
Access parameters for sub-register PLL_CF_START in register PLL_CF
Definition at line 283 of file at86rf212.h.
| #define SR_PLL_DCU_START 0x1b,0x80,7 |
Access parameters for sub-register PLL_DCU_START in register PLL_DCU
Definition at line 287 of file at86rf212.h.
| #define SR_PLL_UNLOCK 0xf,0x3,0 |
Access parameters for sub-register PLL_UNLOCK in register IRQ_STATUS
Definition at line 213 of file at86rf212.h.
| #define SR_RF_MC 0x19,0xf0,4 |
Access parameters for sub-register RF_MC in register RF_CTRL_1
Definition at line 279 of file at86rf212.h.
| #define SR_RND_VALUE 0x6,0x60,5 |
Access parameters for sub-register RND_VALUE in register PHY_RSSI
Definition at line 139 of file at86rf212.h.
| #define SR_RSSI 0x6,0x1f,0 |
Access parameters for sub-register RSSI in register PHY_RSSI
Definition at line 141 of file at86rf212.h.
| #define SR_RX_BL_CTRL 0x4,0x10,4 |
Access parameters for sub-register RX_BL_CTRL in register TRX_CTRL_1
Definition at line 121 of file at86rf212.h.
| #define SR_RX_CRC_VALID 0x6,0x80,7 |
Access parameters for sub-register RX_CRC_VALID in register PHY_RSSI
Definition at line 137 of file at86rf212.h.
| #define SR_RX_PDT_DIS 0x15,0x80,7 |
Access parameters for sub-register RX_PDT_DIS in register RX_SYN
Definition at line 251 of file at86rf212.h.
| #define SR_RX_PDT_LEVEL 0x15,0xf,0 |
Access parameters for sub-register RX_PDT_LEVEL in register RX_SYN
Definition at line 253 of file at86rf212.h.
| #define SR_RX_SAFE_MODE 0xc,0x80,7 |
Access parameters for sub-register RX_SAFE_MODE in register TRX_CTRL_2
Definition at line 165 of file at86rf212.h.
| #define SR_RX_START 0xf,0x4,2 |
Access parameters for sub-register RX_START in register IRQ_STATUS
Definition at line 211 of file at86rf212.h.
| #define SR_SFD_VALUE 0xb,0xff,0 |
Access parameters for sub-register SFD_VALUE in register SFD_VALUE
Definition at line 161 of file at86rf212.h.
| #define SR_SHORT_ADDR_0 0x20,0xff,0 |
Access parameters for sub-register SHORT_ADDR_0 in register SHORT_ADDR_0
Definition at line 309 of file at86rf212.h.
| #define SR_SHORT_ADDR_1 0x21,0xff,0 |
Access parameters for sub-register SHORT_ADDR_1 in register SHORT_ADDR_1
Definition at line 313 of file at86rf212.h.
| #define SR_SPI_CMD_MODE 0x4,0xc,2 |
Access parameters for sub-register SPI_CMD_MODE in register TRX_CTRL_1
Definition at line 123 of file at86rf212.h.
| #define SR_SUB_MODE 0xc,0x4,2 |
Access parameters for sub-register SUB_MODE in register TRX_CTRL_2
Definition at line 171 of file at86rf212.h.
| #define SR_TRAC_STATUS 0x2,0xe0,5 |
Access parameters for sub-register TRAC_STATUS in register TRX_STATE
Definition at line 75 of file at86rf212.h.
| #define SR_TRX_CMD 0x2,0x1f,0 |
Access parameters for sub-register TRX_CMD in register TRX_STATE
Definition at line 83 of file at86rf212.h.
| #define SR_TRX_END 0xf,0x8,3 |
Access parameters for sub-register TRX_END in register IRQ_STATUS
Definition at line 209 of file at86rf212.h.
| #define SR_TRX_OFF_AVDD_EN 0xc,0x40,6 |
Access parameters for sub-register TRX_OFF_AVDD_EN in register TRX_CTRL_2
Definition at line 167 of file at86rf212.h.
| #define SR_TRX_STATUS 0x1,0x1f,0 |
Access parameters for sub-register TRX_STATUS in register TRX_STATUS
Definition at line 57 of file at86rf212.h.
| #define SR_TRX_UR 0xf,0x40,6 |
Access parameters for sub-register TRX_UR in register IRQ_STATUS
Definition at line 203 of file at86rf212.h.
| #define SR_TX_AUTO_CRC_ON 0x4,0x20,5 |
Access parameters for sub-register TX_AUTO_CRC_ON in register TRX_CTRL_1
Definition at line 119 of file at86rf212.h.
| #define SR_TX_PWR 0x5,0x1f,0 |
Access parameters for sub-register TX_PWR in register PHY_TX_PWR
Definition at line 133 of file at86rf212.h.
| #define SR_VERSION_NUM 0x1d,0xff,0 |
Access parameters for sub-register VERSION_NUM in register VERSION_NUM
Definition at line 296 of file at86rf212.h.
| #define SR_XTAL_MODE 0x12,0xf0,4 |
Access parameters for sub-register XTAL_MODE in register XOSC_CTRL
Definition at line 235 of file at86rf212.h.
| #define SR_XTAL_TRIM 0x12,0xf,0 |
Access parameters for sub-register XTAL_TRIM in register XOSC_CTRL
Definition at line 237 of file at86rf212.h.
| #define TRAC_CHANNEL_ACCESS_FAILURE (3) |
TX ARET status for unsuccessful transmission due to no channel access
Definition at line 444 of file at86rf212.h.
| #define TRAC_CHANNEL_ACCESS_FAILURE (3) |
TX ARET status for unsuccessful transmission due to no channel access
Definition at line 444 of file at86rf212.h.
| #define TRAC_NO_ACK (5) |
TX ARET status for unsuccessful transmission due no ACK frame was received
Definition at line 446 of file at86rf212.h.
| #define TRAC_NO_ACK (5) |
TX ARET status for unsuccessful transmission due no ACK frame was received
Definition at line 446 of file at86rf212.h.
| #define TRAC_SUCCESS (0) |
TX ARET status for successful transmission
Definition at line 442 of file at86rf212.h.
| #define TRAC_SUCCESS (0) |
TX ARET status for successful transmission
Definition at line 442 of file at86rf212.h.
| #define TRX_CCA_TIME_US (140) |
duration of a CCA measurement
Definition at line 415 of file at86rf212.h.
| #define TRX_CMD_FR (_BV(5)) |
SPI command code for frame read
Definition at line 396 of file at86rf212.h.
| #define TRX_CMD_FW (_BV(6) | _BV(5)) |
SPI command code for frame write
Definition at line 394 of file at86rf212.h.
| #define TRX_CMD_RR (_BV(7)) |
SPI command code for register read
Definition at line 392 of file at86rf212.h.
| #define TRX_CMD_RW (_BV(7) | _BV(6)) |
SPI command code for register write
Definition at line 390 of file at86rf212.h.
| #define TRX_CMD_SR (0) |
SPI command code for sram read
Definition at line 400 of file at86rf212.h.
| #define TRX_CMD_SW (_BV(6)) |
SPI command code for sram write
Definition at line 398 of file at86rf212.h.
| #define TRX_INIT_TIME_US (510) |
duration transceiver reaches TRX_OFF for the first time
Definition at line 408 of file at86rf212.h.
| #define TRX_IRQ_AMI _BV(5) |
Mask for AMI interrupt
Definition at line 433 of file at86rf212.h.
| #define TRX_IRQ_BAT_LOW _BV(7) |
Mask for battery low interrupt
Definition at line 439 of file at86rf212.h.
| #define TRX_IRQ_CCA_ED _BV(4) |
Mask for CCA_ED interrupt
Definition at line 430 of file at86rf212.h.
| #define TRX_IRQ_PLL_LOCK _BV(0) |
Mask for PLL lock interrupt
Definition at line 418 of file at86rf212.h.
| #define TRX_IRQ_PLL_UNLOCK _BV(1) |
Mask for PLL unlock interrupt
Definition at line 421 of file at86rf212.h.
| #define TRX_IRQ_RX_START _BV(2) |
Mask for RX Start interrupt
Definition at line 424 of file at86rf212.h.
| #define TRX_IRQ_TRX_END _BV(3) |
Mask for RX/TX end interrupt
Definition at line 427 of file at86rf212.h.
| #define TRX_IRQ_UR _BV(6) |
Mask for RX/TX underrun interrupt
Definition at line 436 of file at86rf212.h.
| #define TRX_MAX_CHANNEL (10) |
highest supported channel number
Definition at line 453 of file at86rf212.h.
| #define TRX_MIN_CHANNEL (0) |
lowest supported channel number
Definition at line 450 of file at86rf212.h.
| #define TRX_NB_CHANNELS (11) |
number of channels
Definition at line 456 of file at86rf212.h.
| #define TRX_PLL_LOCK_TIME_US (180) |
maximum duration, which PLL needs to lock
Definition at line 411 of file at86rf212.h.
| #define TRX_RESET_TIME_US (6) |
duration while reset=low is asserted
Definition at line 405 of file at86rf212.h.
| #define TRX_SUPPORTED_CHANNELS (0x00007ffUL) |
Mask for supported channels of this radio. The AT86RF212 supports channels 0 ... 10 of IEEE 802.15.4 (currently no support for free configurable frequencies here).
Definition at line 463 of file at86rf212.h.
| #define TRX_SUPPORTED_PAGES (42) |
Mask for supported channel pages (a.k.a. modulation schemes) of this radio. The AT86RF230 supports channel page ???? OQPSK_250.
Definition at line 469 of file at86rf212.h.
1.5.5