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at86rf212.h

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/* THIS FILE IS GENERATED by ds2reg.py FROM INPUT Templates/at86rf212.txt */

/* Copyright (c) 2008 Axel Wachtler
   All rights reserved.

   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions
   are met:

   * Redistributions of source code must retain the above copyright
     notice, this list of conditions and the following disclaimer.
   * Redistributions in binary form must reproduce the above copyright
     notice, this list of conditions and the following disclaimer in the
     documentation and/or other materials provided with the distribution.
   * Neither the name of the authors nor the names of its contributors
     may be used to endorse or promote products derived from this software
     without specific prior written permission.

   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */

/* $Id: at86rf212_8h-source.html,v 1.1.1.1 2010/01/21 21:37:02 awachtler Exp $ */
#ifndef AT86RF212_H
#define AT86RF212_H (1)
/* === Includes ============================================================== */

/* === Externals ============================================================= */

/* === Types ================================================================= */

typedef uint8_t trx_ramaddr_t;
typedef uint8_t trx_regval_t;
typedef uint8_t trx_regaddr_t;

/* === Macros ================================================================ */
#define RG_TRX_STATUS (0x1)

  #define SR_CCA_DONE 0x1,0x80,7

  #define SR_CCA_STATUS 0x1,0x40,6

  #define SR_TRX_STATUS 0x1,0x1f,0
    #define P_ON (0)
    #define BUSY_RX (1)
    #define BUSY_TX (2)
    #define RX_ON (6)
    #define TRX_OFF (8)
    #define PLL_ON (9)
    #define SLEEP (15)
    #define BUSY_RX_AACK (17)
    #define BUSY_TX_ARET (18)
    #define RX_AACK_ON (22)
    #define TX_ARET_ON (25)
    #define RX_ON_NOCLK (28)
    #define RX_AACK_ON_NOCLK (29)
    #define BUSY_RX_AACK_NOCLK (30)

#define RG_TRX_STATE (0x2)

  #define SR_TRAC_STATUS 0x2,0xe0,5
    #define TRAC_SUCCESS (0)
    #define TRAC_SUCCESS_DATA_PENDING (1)
    #define TRAC_SUCCESS_WAIT_FOR_ACK (2)
    #define TRAC_CHANNEL_ACCESS_FAILURE (3)
    #define TRAC_NO_ACK (5)
    #define TRAC_INVALID (7)

  #define SR_TRX_CMD 0x2,0x1f,0
    #define CMD_NOP (0)
    #define CMD_TX_START (2)
    #define CMD_FORCE_TRX_OFF (3)
    #define CMD_RX_ON (6)
    #define CMD_TRX_OFF (8)
    #define CMD_PLL_ON (9)
    #define CMD_RX_AACK_ON (22)
    #define CMD_TX_ARET_ON (25)

#define RG_TRX_CTRL_0 (0x3)

  #define SR_PAD_IO 0x3,0xc0,6

  #define SR_PAD_IO_CLKM 0x3,0x30,4
    #define CLKM_2mA (0)
    #define CLKM_4mA (1)
    #define CLKM_6mA (2)
    #define CLKM_8mA (3)

  #define SR_CLKM_SHA_SEL 0x3,0x8,3

  #define SR_CLKM_CTRL 0x3,0x7,0
    #define CLKM_no_clock (0)
    #define CLKM_1MHz (1)
    #define CLKM_2MHz (2)
    #define CLKM_4MHz (3)
    #define CLKM_8MHz (4)
    #define CLKM_16MHz (5)

#define RG_TRX_CTRL_1 (0x4)

  #define SR_PA_EXT_EN 0x4,0x80,7

  #define SR_IRQ_2_EXT_EN 0x4,0x40,6

  #define SR_TX_AUTO_CRC_ON 0x4,0x20,5

  #define SR_RX_BL_CTRL 0x4,0x10,4

  #define SR_SPI_CMD_MODE 0x4,0xc,2

  #define SR_IRQ_MASK_MODE 0x4,0x3,0

#define RG_PHY_TX_PWR (0x5)

  #define SR_PA_BOOST 0x5,0x80,7

  #define SR_GC_PA 0x5,0x60,5

  #define SR_TX_PWR 0x5,0x1f,0

#define RG_PHY_RSSI (0x6)

  #define SR_RX_CRC_VALID 0x6,0x80,7

  #define SR_RND_VALUE 0x6,0x60,5

  #define SR_RSSI 0x6,0x1f,0

#define RG_PHY_ED_LEVEL (0x7)

  #define SR_ED_LEVEL 0x7,0xff,0

#define RG_PHY_CC_CCA (0x8)

  #define SR_CCA_REQUEST 0x8,0x80,7

  #define SR_CCA_MODE 0x8,0x60,5

  #define SR_CHANNEL 0x8,0x1f,0

#define RG_CCA_THRES (0x9)

  #define SR_CCA_ED_THRES 0x9,0xf,0

#define RG_SFD_VALUE (0xb)

  #define SR_SFD_VALUE 0xb,0xff,0

#define RG_TRX_CTRL_2 (0xc)

  #define SR_RX_SAFE_MODE 0xc,0x80,7

  #define SR_TRX_OFF_AVDD_EN 0xc,0x40,6

  #define SR_BPSK_OQPSK 0xc,0x8,3

  #define SR_SUB_MODE 0xc,0x4,2

  #define SR_OQPSK_DATA_RATE 0xc,0x3,0

#define RG_ANT_DIV (0xd)

  #define SR_ANT_SEL 0xd,0x80,7

  #define SR_ANT_EXT_SW_EN 0xd,0x4,2

  #define SR_ANT_CTRL 0xd,0x3,0

#define RG_IRQ_MASK (0xe)

  #define SR_MASK_BAT_LOW 0xe,0x80,7

  #define SR_MASK_TRX_UR 0xe,0x40,6

  #define SR_MASK_AMI 0xe,0x20,5

  #define SR_MASK_CCA_ED_READY 0xe,0x10,4

  #define SR_MASK_TRX_END 0xe,0x8,3

  #define SR_MASK_RX_START 0xe,0x4,2

  #define SR_MASK_PLL_UNLOCK 0xe,0x3,0

#define RG_IRQ_STATUS (0xf)

  #define SR_BAT_LOW 0xf,0x80,7

  #define SR_TRX_UR 0xf,0x40,6

  #define SR_AMI 0xf,0x20,5

  #define SR_CCA_ED_READY 0xf,0x10,4

  #define SR_TRX_END 0xf,0x8,3

  #define SR_RX_START 0xf,0x4,2

  #define SR_PLL_UNLOCK 0xf,0x3,0

#define RG_VREG_CTRL (0x10)

  #define SR_AVREG_EXT 0x10,0x80,7

  #define SR_AVDD_OK 0x10,0x40,6

  #define SR_DVREG_EXT 0x10,0x8,3

  #define SR_DVDD_OK 0x10,0x4,2

#define RG_BATMON (0x11)

  #define SR_BATMON_OK 0x11,0x20,5

  #define SR_BATMON_HR 0x11,0x10,4

  #define SR_BATMON_VTH 0x11,0xf,0

#define RG_XOSC_CTRL (0x12)

  #define SR_XTAL_MODE 0x12,0xf0,4

  #define SR_XTAL_TRIM 0x12,0xf,0

#define RG_CC_CTRL_0 (0x13)

  #define SR_CC_NUMBER 0x13,0xff,0

#define RG_CC_CTRL_1 (0x14)

  #define SR_CC_BAND 0x14,0x4,2

  #define SR_CC_ 0x14,0x3,0

#define RG_RX_SYN (0x15)

  #define SR_RX_PDT_DIS 0x15,0x80,7

  #define SR_RX_PDT_LEVEL 0x15,0xf,0

#define RG_RF_CTRL_0 (0x16)

  #define SR_PA_LT 0x16,0xc0,6

  #define SR_GC_TX_OFFS 0x16,0x3,0

#define RG_XAH_CTRL_1 (0x17)

  #define SR_CSMA_LBT_MODE 0x17,0x80,7

  #define SR_AACK_FLTR_RES_FT 0x17,0x20,5

  #define SR_AACK_UPLD_RES_FT 0x17,0x10,4

  #define SR_AACK_ACK_TIME 0x17,0x4,2

  #define SR_AACK_PROM_MODE 0x17,0x3,0

#define RG_FTN_CTRL (0x18)

  #define SR_FTN_START 0x18,0x80,7

#define RG_RF_CTRL_1 (0x19)

  #define SR_RF_MC 0x19,0xf0,4

#define RG_PLL_CF (0x1a)

  #define SR_PLL_CF_START 0x1a,0x80,7

#define RG_PLL_DCU (0x1b)

  #define SR_PLL_DCU_START 0x1b,0x80,7

#define RG_PART_NUM (0x1c)

  #define SR_PART_NUM 0x1c,0xff,0
    #define RF212A_PART_NUM (7)

#define RG_VERSION_NUM (0x1d)

  #define SR_VERSION_NUM 0x1d,0xff,0
    #define RF212A_VERSION_NUM (1)

#define RG_MAN_ID_0 (0x1e)

  #define SR_MAN_ID_0 0x1e,0xff,0

#define RG_MAN_ID_1 (0x1f)

  #define SR_MAN_ID_1 0x1f,0xff,0

#define RG_SHORT_ADDR_0 (0x20)

  #define SR_SHORT_ADDR_0 0x20,0xff,0

#define RG_SHORT_ADDR_1 (0x21)

  #define SR_SHORT_ADDR_1 0x21,0xff,0

#define RG_PAN_ID_0 (0x22)

  #define SR_PAN_ID_0 0x22,0xff,0

#define RG_PAN_ID_1 (0x23)

  #define SR_PAN_ID_1 0x23,0xff,0

#define RG_IEEE_ADDR_0 (0x24)

  #define SR_IEEE_ADDR_0 0x24,0xff,0

#define RG_IEEE_ADDR_1 (0x25)

  #define SR_IEEE_ADDR_1 0x25,0xff,0

#define RG_IEEE_ADDR_2 (0x26)

  #define SR_IEEE_ADDR_2 0x26,0xff,0

#define RG_IEEE_ADDR_3 (0x27)

  #define SR_IEEE_ADDR_3 0x27,0xff,0

#define RG_IEEE_ADDR_4 (0x28)

  #define SR_IEEE_ADDR_4 0x28,0xff,0

#define RG_IEEE_ADDR_5 (0x29)

  #define SR_IEEE_ADDR_5 0x29,0xff,0

#define RG_IEEE_ADDR_6 (0x2a)

  #define SR_IEEE_ADDR_6 0x2a,0xff,0

#define RG_IEEE_ADDR_7 (0x2b)

  #define SR_IEEE_ADDR_7 0x2b,0xff,0

#define RG_XAH_CTRL_0 (0x2c)

  #define SR_MAX_FRAME_RETRIES 0x2c,0xf0,4

  #define SR_MAX_CSMA_RETRIES 0x2c,0xf,0

#define RG_CSMA_SEED_0 (0x2d)

  #define SR_CSMA_SEED_0 0x2d,0xff,0

#define RG_CSMA_SEED_1 (0x2e)

  #define SR_AACK_FVN_MODE 0x2e,0xc0,6

  #define SR_AACK_SET_PD 0x2e,0x20,5

  #define SR_AACK_DIS_ACK 0x2e,0x10,4

  #define SR_AACK_I_AM_COORD 0x2e,0x8,3

  #define SR_CSMA_SEED_1 0x2e,0x7,0

#define RG_CSMA_BE (0x2f)

  #define SR_MAX_BE 0x2f,0xf0,4

  #define SR_MIN_BE 0x2f,0xf,0

#define RADIO_NAME "AT86RF212"

#define RADIO_PART_NUM (RF212A_PART_NUM)

#define RADIO_VERSION_NUM (RF212A_VERSION_NUM)

#define TRX_CMD_RW           (_BV(7) | _BV(6))

#define TRX_CMD_RR           (_BV(7))

#define TRX_CMD_FW           (_BV(6) | _BV(5))

#define TRX_CMD_FR           (_BV(5))

#define TRX_CMD_SW           (_BV(6))

#define TRX_CMD_SR           (0)

#define TRX_CMD_RADDR_MASK   (0x3f)

#define TRX_RESET_TIME_US    (6)

#define TRX_INIT_TIME_US     (510)

#define TRX_PLL_LOCK_TIME_US     (180)


#define TRX_CCA_TIME_US     (140)

#define TRX_IRQ_PLL_LOCK   _BV(0)

#define TRX_IRQ_PLL_UNLOCK _BV(1)

#define TRX_IRQ_RX_START   _BV(2)

#define TRX_IRQ_TRX_END    _BV(3)

#define TRX_IRQ_CCA_ED     _BV(4)

#define TRX_IRQ_AMI        _BV(5)

#define TRX_IRQ_UR         _BV(6)

#define TRX_IRQ_BAT_LOW    _BV(7)

#define TRAC_SUCCESS (0)

#define TRAC_CHANNEL_ACCESS_FAILURE (3)

#define TRAC_NO_ACK (5)


#define TRX_MIN_CHANNEL (0)

#define TRX_MAX_CHANNEL (10)

#define TRX_NB_CHANNELS (11)

#define TRX_SUPPORTED_CHANNELS  (0x00007ffUL)

#define TRX_SUPPORTED_PAGES     (42)
#define TRX_SUPPORTS_BAND_700 (1)
#define TRX_SUPPORTS_BAND_800 (1)
#define TRX_SUPPORTS_BAND_900 (1)

#define RATE_CODE_BPSK20    (0)

#define RATE_CODE_BPSK40    (4)

#define RATE_CODE_OQPSK100  (8)

#define RATE_CODE_OQPSK200  (9)

#define RATE_CODE_OQPSK400  (10)
#define RATE_CODE_OQPSK400_1  (11)

#define RATE_CODE_OQPSK250  (12)

#define RATE_CODE_OQPSK500  (13)

#define RATE_CODE_OQPSK1000 (14)
#define RATE_CODE_OQPSK1000_1 (15)

#define RATE_CODE_NONE      (255)

#endif /* ifndef AT86RF212_H */

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