Atmel REB-CBB with Radio Extender Board (REB) attached Any type of REB is supported. More...
Go to the source code of this file.
Defines | |
#define | DDR_KEY PORTB_DIR |
#define | DEFAULT_SPI_RATE (SPI_RATE_1_2) |
#define | DI_TRX_IRQ() {PORTC.INT0MASK &= ~TRX_IRQ;} |
#define | EI_TRX_IRQ() {PORTC.INT0MASK |= TRX_IRQ;} |
#define | HIF_TYPE (HIF_UART_0) |
#define | HWTIMER_REG (TCD0.CNT) |
#define | HWTIMER_TICK ((1.0*HWTMR_PRESCALE)/F_CPU) |
#define | HWTIMER_TICK_NB (0xFFFFUL) |
#define | HWTMR_PRESCALE (1) |
#define | INVERSE_KEYS (1) |
#define | KEY_INIT() do{ PORTB_PIN3CTRL = PORT_OPC_PULLUP_gc; DDR_KEY &= ~MASK_KEY; }while(0) |
#define | LED_DDR PORTB_DIR |
#define | LED_MASK (0x07) |
#define | LED_NUMBER (3) |
#define | LED_PORT PORTB_OUT |
#define | LED_SHIFT (0) |
#define | LEDS_INVERSE (0) |
#define | MASK_KEY (0x08) |
#define | MASK_TRX_RESET (_BV(0)) |
#define | MASK_TRX_SLPTR (_BV(3)) |
#define | PIN_KEY PORTB_IN |
#define | PORT_KEY PORTB_OUT |
#define | PORT_SPI (PORTC) |
#define | PORT_TRX_RESET PORTC |
#define | PORT_TRX_SLPTR PORTC |
#define | SHIFT_KEY (3) |
#define | SLEEP_ON_KEY() |
#define | SLEEP_ON_KEY_INIT() do{}while(0) |
#define | SLEEP_ON_KEY_vect PORTB_INT0_vect |
#define | SPI_DATA_REG SPIC.DATA |
#define | SPI_MISO _BV(6) |
#define | SPI_MOSI _BV(5) |
#define | SPI_SCK _BV(7) |
#define | SPI_SELN_HIGH() PORT_SPI.OUTSET = SPI_SS; SREG = sreg |
#define | SPI_SELN_LOW() uint8_t sreg = SREG; cli(); PORT_SPI.OUTCLR = SPI_SS |
#define | SPI_SS _BV(4) |
#define | SPI_WAITFOR() do { while((SPIC.STATUS & SPI_IF_bm) == 0);} while(0) |
#define | TIMER_INIT() |
#define | TIMER_IRQ_vect TCD0_OVF_vect |
#define | TIMER_POOL_SIZE (4) |
#define | TIMER_TICK (HWTIMER_TICK_NB * HWTIMER_TICK) |
#define | TRX_IRQ _BV(2) |
#define | TRX_IRQ_INIT() |
#define | TRX_IRQ_vect PORTC_INT0_vect |
#define | TRX_RESET_HIGH() PORT_TRX_RESET.OUTSET = MASK_TRX_RESET |
#define | TRX_RESET_INIT() PORT_TRX_RESET.DIRSET = MASK_TRX_RESET |
#define | TRX_RESET_LOW() PORT_TRX_RESET.OUTCLR = MASK_TRX_RESET |
#define | TRX_SLPTR_HIGH() PORT_TRX_SLPTR.OUTSET = MASK_TRX_SLPTR |
#define | TRX_SLPTR_INIT() PORT_TRX_SLPTR.DIRSET = MASK_TRX_SLPTR |
#define | TRX_SLPTR_LOW() PORT_TRX_SLPTR.OUTCLR = MASK_TRX_SLPTR |
#define | TRX_TSTAMP_REG TCD0.CNT |
Atmel REB-CBB with Radio Extender Board (REB) attached Any type of REB is supported.
The wiring of the REB and the MCU is shown below:
ATxmega256A3 AT86RF2XX ------------ --------- PC0 RSTN PC1 DIG2 PC2 IRQ PC3 SLPTR PC4 SELN PC5 MOSI PC6 MISO PC7 SCK PD0 CLKM PD1 TXCW
PB0 LED1 PB1 LED2 PB2 LED3 PB3 KEY1
#define DI_TRX_IRQ | ( | ) | {PORTC.INT0MASK &= ~TRX_IRQ;} |
disable TRX interrupt
#define EI_TRX_IRQ | ( | ) | {PORTC.INT0MASK |= TRX_IRQ;} |
enable TRX interrupt
#define MASK_TRX_RESET (_BV(0)) |
PIN mask for RESET pin
#define MASK_TRX_SLPTR (_BV(3)) |
PIN mask for SLP_TR pin
#define PORT_SPI (PORTC) |
PORT register for SPI port
#define PORT_TRX_RESET PORTC |
PORT register for RESET pin
#define PORT_TRX_SLPTR PORTC |
DDR register for SLP_TR pin
#define SLEEP_ON_KEY | ( | ) |
do{\ } while(0)
#define SPI_DATA_REG SPIC.DATA |
abstraction for SPI data register
#define SPI_MISO _BV(6) |
PIN mask for MISO pin
#define SPI_MOSI _BV(5) |
PIN mask for MOSI pin
#define SPI_SCK _BV(7) |
PIN mask for SCK pin
#define SPI_SELN_HIGH | ( | ) | PORT_SPI.OUTSET = SPI_SS; SREG = sreg |
set SS line to high level
#define SPI_SELN_LOW | ( | ) | uint8_t sreg = SREG; cli(); PORT_SPI.OUTCLR = SPI_SS |
set SS line to low level
#define SPI_SS _BV(4) |
PIN mask for SS pin
#define SPI_WAITFOR | ( | ) | do { while((SPIC.STATUS & SPI_IF_bm) == 0);} while(0) |
wait until SPI transfer is ready
#define TIMER_INIT | ( | ) |
do{ \ TCD0.CTRLA = TC_CLKSEL_DIV1_gc; \ TCD0.INTFLAGS |= TC0_OVFIF_bm; \ TCD0.INTCTRLA = TC_OVFINTLVL_HI_gc; \ }while(0)
#define TRX_IRQ _BV(2) |
interrupt mask for PORTC
#define TRX_IRQ_INIT | ( | ) |
do{\ PORTC.INT0MASK = TRX_IRQ; \ PORTC.INTCTRL = PORT_INT0LVL_HI_gc; \ PMIC.CTRL |= PMIC_HILVLEN_bm;\ } while(0)
init interrupt handling
#define TRX_IRQ_vect PORTC_INT0_vect |
interrupt vector name
#define TRX_RESET_HIGH | ( | ) | PORT_TRX_RESET.OUTSET = MASK_TRX_RESET |
set RESET pin to high level
#define TRX_RESET_INIT | ( | ) | PORT_TRX_RESET.DIRSET = MASK_TRX_RESET |
RESET pin IO initialization
#define TRX_RESET_LOW | ( | ) | PORT_TRX_RESET.OUTCLR = MASK_TRX_RESET |
set RESET pin to low level
#define TRX_SLPTR_HIGH | ( | ) | PORT_TRX_SLPTR.OUTSET = MASK_TRX_SLPTR |
set SLP_TR pin to high level set SLP_TR pin to low level
#define TRX_SLPTR_INIT | ( | ) | PORT_TRX_SLPTR.DIRSET = MASK_TRX_SLPTR |
SLP_TR pin IO initialization
#define TRX_TSTAMP_REG TCD0.CNT |
timestamp register for RX_START event FIXME: add and test the enabling of input capture for separate RX_START (AT86RF231/212) currently we use the timer register.