board_cbb2xx.h

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00001 /* Copyright (c) 2011 Axel Wachtler, Daniel Thiele
00002    All rights reserved.
00003 
00004    Redistribution and use in source and binary forms, with or without
00005    modification, are permitted provided that the following conditions
00006    are met:
00007 
00008    * Redistributions of source code must retain the above copyright
00009      notice, this list of conditions and the following disclaimer.
00010    * Redistributions in binary form must reproduce the above copyright
00011      notice, this list of conditions and the following disclaimer in the
00012      documentation and/or other materials provided with the distribution.
00013    * Neither the name of the authors nor the names of its contributors
00014      may be used to endorse or promote products derived from this software
00015      without specific prior written permission.
00016 
00017    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00018    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00019    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00020    ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
00021    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
00022    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
00023    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00024    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
00025    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
00026    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00027    POSSIBILITY OF SUCH DAMAGE. */
00028 
00029 /* $Id: board__cbb2xx_8h_source.html,v 1.1.1.4 2013/04/09 21:11:49 awachtler Exp $ */
00058 #ifndef BOARD_CBB2XX_H
00059 #define BOARD_CBB2XX_H
00060 
00061 #if defined(cbb230)
00062 # define BOARD_TYPE BOARD_CBB230
00063 # define BOARD_NAME "cbb230"
00064 # define RADIO_TYPE (RADIO_AT86RF230A)
00065 #elif defined(cbb230b)
00066 # define BOARD_TYPE BOARD_CBB230B
00067 # define BOARD_NAME "cbb230b"
00068 # define RADIO_TYPE (RADIO_AT86RF230B)
00069 #elif defined(cbb231)
00070 # define BOARD_TYPE BOARD_CBB231
00071 # define BOARD_NAME "cbb231"
00072 # define RADIO_TYPE (RADIO_AT86RF231)
00073 #elif defined(cbb212)
00074 # define BOARD_TYPE BOARD_CBB212
00075 # define BOARD_NAME "cbb212"
00076 # define RADIO_TYPE (RADIO_AT86RF212)
00077 #elif defined(cbb232)
00078 # define BOARD_TYPE BOARD_CBB232
00079 # define BOARD_NAME "cbb232"
00080 # define RADIO_TYPE (RADIO_AT86RF232)
00081 #elif defined(cbb233)
00082 # define BOARD_TYPE BOARD_CBB233
00083 # define BOARD_NAME "cbb233"
00084 # define RADIO_TYPE (RADIO_AT86RF233)
00085 #endif
00086 
00087 #ifndef DEFAULT_SPI_RATE
00088 # define DEFAULT_SPI_RATE  (SPI_RATE_1_2)
00089 #endif
00090 
00091 /*=== Hardware Components ============================================*/
00092 
00093 /*=== TRX pin access macros ==========================================*/
00094 
00095 #define PORT_TRX_RESET  PORTC         
00096 #define MASK_TRX_RESET  (_BV(0))      
00098 #define TRX_RESET_INIT() PORT_TRX_RESET.DIRSET = MASK_TRX_RESET    
00099 #define TRX_RESET_HIGH() PORT_TRX_RESET.OUTSET = MASK_TRX_RESET   
00100 #define TRX_RESET_LOW()  PORT_TRX_RESET.OUTCLR = MASK_TRX_RESET  
00102 #define PORT_TRX_SLPTR  PORTC         
00103 #define MASK_TRX_SLPTR  (_BV(3))    
00106 #define TRX_SLPTR_INIT() PORT_TRX_SLPTR.DIRSET = MASK_TRX_SLPTR
00107 
00108 #define TRX_SLPTR_HIGH() PORT_TRX_SLPTR.OUTSET = MASK_TRX_SLPTR
00109 
00110 #define TRX_SLPTR_LOW()  PORT_TRX_SLPTR.OUTCLR = MASK_TRX_SLPTR
00111 
00112 
00113 /*=== IRQ access macros ==============================================*/
00114 # define TRX_IRQ_vect    PORTC_INT0_vect    
00115 # define TRX_IRQ         _BV(2)    
00121 # define TRX_IRQ_INIT()  do{\
00122                             PORTC.INT0MASK = TRX_IRQ; \
00123                             PORTC.INTCTRL = PORT_INT0LVL_HI_gc; \
00124                             PMIC.CTRL |= PMIC_HILVLEN_bm;\
00125                           } while(0)
00126 
00128 #define DI_TRX_IRQ() {PORTC.INT0MASK &= ~TRX_IRQ;}
00129 
00131 #define EI_TRX_IRQ() {PORTC.INT0MASK |= TRX_IRQ;}
00132 
00137 #define TRX_TSTAMP_REG TCD0.CNT
00138 
00139 /*=== SPI access macros ==============================================*/
00140 #define PORT_SPI (PORTC)  
00142 #define SPI_MOSI _BV(5)  
00143 #define SPI_MISO _BV(6)  
00144 #define SPI_SCK  _BV(7)  
00145 #define SPI_SS   _BV(4)  
00147 #define SPI_DATA_REG SPIC.DATA  
00153 static inline void SPI_INIT(uint8_t spirate)
00154 {
00155     /* first configure SPI Port, then SPCR */
00156     PORT_SPI.OUTSET = SPI_SCK | SPI_SS;
00157     PORT_SPI.DIRSET = SPI_MOSI | SPI_SCK | SPI_SS;
00158     PORT_SPI.DIRCLR = SPI_MISO;
00159 
00160     SPIC.CTRL = SPI_ENABLE_bm | SPI_MASTER_bm;
00161 
00162     SPIC.CTRL |= (spirate & 0x03);
00163     SPIC.CTRL |= ((spirate << 5) & 0x80); /* CLK2X */
00164 }
00165 
00167 #define SPI_SELN_LOW()       uint8_t sreg = SREG; cli(); PORT_SPI.OUTCLR = SPI_SS
00168 
00169 #define SPI_SELN_HIGH()      PORT_SPI.OUTSET = SPI_SS; SREG = sreg
00170 
00171 #define SPI_WAITFOR()        do { while((SPIC.STATUS & SPI_IF_bm) == 0);} while(0)
00172 
00173 
00174 /*=== LED access macros ==============================================*/
00175 #define LED_PORT     PORTB_OUT
00176 #define LED_DDR      PORTB_DIR
00177 #define LED_MASK     (0x07)
00178 #define LED_SHIFT    (0)
00179 #define LEDS_INVERSE (0)
00180 #define LED_NUMBER   (3)
00181 
00182 /*=== KEY access macros ==============================================*/
00183 #define PORT_KEY     PORTB_OUT
00184 #define PIN_KEY      PORTB_IN
00185 #define DDR_KEY      PORTB_DIR
00186 #define MASK_KEY     (0x08)
00187 #define SHIFT_KEY    (3)
00188 #define INVERSE_KEYS (1)
00189 
00190 #define KEY_INIT() do{ PORTB_PIN3CTRL = PORT_OPC_PULLUP_gc; DDR_KEY &= ~MASK_KEY; }while(0)
00191 
00192 #define SLEEP_ON_KEY_INIT() do{}while(0)
00193 #define SLEEP_ON_KEY() \
00194         do{\
00195         } while(0)
00196 
00197 #define SLEEP_ON_KEY_vect PORTB_INT0_vect
00198 
00199 /*=== Host Interface ================================================*/
00200 #define HIF_TYPE (HIF_UART_0)
00201 
00202 /*=== TIMER Interface ===============================================*/
00203 #define HWTMR_PRESCALE  (1)
00204 #define HWTIMER_TICK    ((1.0*HWTMR_PRESCALE)/F_CPU)
00205 #define HWTIMER_TICK_NB (0xFFFFUL)
00206 #define HWTIMER_REG     (TCD0.CNT)
00207 #define TIMER_TICK      (HWTIMER_TICK_NB * HWTIMER_TICK)
00208 #define TIMER_POOL_SIZE (4)
00209 #define TIMER_INIT() \
00210     do{ \
00211         TCD0.CTRLA = TC_CLKSEL_DIV1_gc; \
00212         TCD0.INTFLAGS |= TC0_OVFIF_bm; \
00213         TCD0.INTCTRLA = TC_OVFINTLVL_HI_gc; \
00214     }while(0)
00215 #define TIMER_IRQ_vect   TCD0_OVF_vect
00216 
00217 #endif /* BOARD_CBB2XX_H */

This documentation for µracoli was generated on Tue Apr 9 2013 by  doxygen 1.7.1