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00058 #ifndef BOARD_CBB2XX_H
00059 #define BOARD_CBB2XX_H
00060
00061 #if defined(cbb230)
00062 # define BOARD_TYPE BOARD_CBB230
00063 # define BOARD_NAME "cbb230"
00064 # define RADIO_TYPE (RADIO_AT86RF230A)
00065 #elif defined(cbb230b)
00066 # define BOARD_TYPE BOARD_CBB230B
00067 # define BOARD_NAME "cbb230b"
00068 # define RADIO_TYPE (RADIO_AT86RF230B)
00069 #elif defined(cbb231)
00070 # define BOARD_TYPE BOARD_CBB231
00071 # define BOARD_NAME "cbb231"
00072 # define RADIO_TYPE (RADIO_AT86RF231)
00073 #elif defined(cbb212)
00074 # define BOARD_TYPE BOARD_CBB212
00075 # define BOARD_NAME "cbb212"
00076 # define RADIO_TYPE (RADIO_AT86RF212)
00077 #elif defined(cbb232)
00078 # define BOARD_TYPE BOARD_CBB232
00079 # define BOARD_NAME "cbb232"
00080 # define RADIO_TYPE (RADIO_AT86RF232)
00081 #elif defined(cbb233)
00082 # define BOARD_TYPE BOARD_CBB233
00083 # define BOARD_NAME "cbb233"
00084 # define RADIO_TYPE (RADIO_AT86RF233)
00085 #endif
00086
00087 #ifndef DEFAULT_SPI_RATE
00088 # define DEFAULT_SPI_RATE (SPI_RATE_1_2)
00089 #endif
00090
00091
00092
00093
00094
00095 #define PORT_TRX_RESET PORTC
00096 #define MASK_TRX_RESET (_BV(0))
00098 #define TRX_RESET_INIT() PORT_TRX_RESET.DIRSET = MASK_TRX_RESET
00099 #define TRX_RESET_HIGH() PORT_TRX_RESET.OUTSET = MASK_TRX_RESET
00100 #define TRX_RESET_LOW() PORT_TRX_RESET.OUTCLR = MASK_TRX_RESET
00102 #define PORT_TRX_SLPTR PORTC
00103 #define MASK_TRX_SLPTR (_BV(3))
00106 #define TRX_SLPTR_INIT() PORT_TRX_SLPTR.DIRSET = MASK_TRX_SLPTR
00107
00108 #define TRX_SLPTR_HIGH() PORT_TRX_SLPTR.OUTSET = MASK_TRX_SLPTR
00109
00110 #define TRX_SLPTR_LOW() PORT_TRX_SLPTR.OUTCLR = MASK_TRX_SLPTR
00111
00112
00113
00114 # define TRX_IRQ_vect PORTC_INT0_vect
00115 # define TRX_IRQ _BV(2)
00121 # define TRX_IRQ_INIT() do{\
00122 PORTC.INT0MASK = TRX_IRQ; \
00123 PORTC.INTCTRL = PORT_INT0LVL_HI_gc; \
00124 PMIC.CTRL |= PMIC_HILVLEN_bm;\
00125 } while(0)
00126
00128 #define DI_TRX_IRQ() {PORTC.INT0MASK &= ~TRX_IRQ;}
00129
00131 #define EI_TRX_IRQ() {PORTC.INT0MASK |= TRX_IRQ;}
00132
00137 #define TRX_TSTAMP_REG TCD0.CNT
00138
00139
00140 #define PORT_SPI (PORTC)
00142 #define SPI_MOSI _BV(5)
00143 #define SPI_MISO _BV(6)
00144 #define SPI_SCK _BV(7)
00145 #define SPI_SS _BV(4)
00147 #define SPI_DATA_REG SPIC.DATA
00153 static inline void SPI_INIT(uint8_t spirate)
00154 {
00155
00156 PORT_SPI.OUTSET = SPI_SCK | SPI_SS;
00157 PORT_SPI.DIRSET = SPI_MOSI | SPI_SCK | SPI_SS;
00158 PORT_SPI.DIRCLR = SPI_MISO;
00159
00160 SPIC.CTRL = SPI_ENABLE_bm | SPI_MASTER_bm;
00161
00162 SPIC.CTRL |= (spirate & 0x03);
00163 SPIC.CTRL |= ((spirate << 5) & 0x80);
00164 }
00165
00167 #define SPI_SELN_LOW() uint8_t sreg = SREG; cli(); PORT_SPI.OUTCLR = SPI_SS
00168
00169 #define SPI_SELN_HIGH() PORT_SPI.OUTSET = SPI_SS; SREG = sreg
00170
00171 #define SPI_WAITFOR() do { while((SPIC.STATUS & SPI_IF_bm) == 0);} while(0)
00172
00173
00174
00175 #define LED_PORT PORTB_OUT
00176 #define LED_DDR PORTB_DIR
00177 #define LED_MASK (0x07)
00178 #define LED_SHIFT (0)
00179 #define LEDS_INVERSE (0)
00180 #define LED_NUMBER (3)
00181
00182
00183 #define PORT_KEY PORTB_OUT
00184 #define PIN_KEY PORTB_IN
00185 #define DDR_KEY PORTB_DIR
00186 #define MASK_KEY (0x08)
00187 #define SHIFT_KEY (3)
00188 #define INVERSE_KEYS (1)
00189
00190 #define KEY_INIT() do{ PORTB_PIN3CTRL = PORT_OPC_PULLUP_gc; DDR_KEY &= ~MASK_KEY; }while(0)
00191
00192 #define SLEEP_ON_KEY_INIT() do{}while(0)
00193 #define SLEEP_ON_KEY() \
00194 do{\
00195 } while(0)
00196
00197 #define SLEEP_ON_KEY_vect PORTB_INT0_vect
00198
00199
00200 #define HIF_TYPE (HIF_UART_0)
00201
00202
00203 #define HWTMR_PRESCALE (1)
00204 #define HWTIMER_TICK ((1.0*HWTMR_PRESCALE)/F_CPU)
00205 #define HWTIMER_TICK_NB (0xFFFFUL)
00206 #define HWTIMER_REG (TCD0.CNT)
00207 #define TIMER_TICK (HWTIMER_TICK_NB * HWTIMER_TICK)
00208 #define TIMER_POOL_SIZE (4)
00209 #define TIMER_INIT() \
00210 do{ \
00211 TCD0.CTRLA = TC_CLKSEL_DIV1_gc; \
00212 TCD0.INTFLAGS |= TC0_OVFIF_bm; \
00213 TCD0.INTCTRLA = TC_OVFINTLVL_HI_gc; \
00214 }while(0)
00215 #define TIMER_IRQ_vect TCD0_OVF_vect
00216
00217 #endif